Control means for an integrated memory matrix display and its control process

ABSTRACT

A control system for an integrated memory matrix display and its associated process is disclosed. The control system for the matrix display utilizes a first group of n row conductors and a second group of m column conductors which carry appropriate signals for excitation of an electro-optical display material at image points which form the integrated memory of a display. A first selection circuit is connected to n&#39; address rows and to n row conductors where n is ≦2 n&#39;  and m read-write circuits, each connected to a column conductor and combine into k packages wherein each package has a maximum of l read-write circuits with the integers m, l and k being such that l is &gt;1 and &lt;m and k is &gt;1 and &lt;m. Each pth read-write circuit of package is connected to the pth row of a bidirectional data bus 21 with l rows, with the p being an integer such that p≧1 and ≦l. Also contained in this system is k processing circuits which are each connected on the one hand to a package of read-write circuits and on the other two a second selection circuit which itself is connected to k&#39; address rows with k being ≦2 k&#39; .

The present invention relates to a control means for an integratedmemory matrix display and to its control process.

The invention more particularly applies to any matrix display with anactive matrix having an electrooptical display material, whereof anoptical property such as opacity, refractive index, transparency,absorption, etc. can be modified with the aid of a random excitation.

The invention particularly advantageously applies to liquid crystalmatrix displays without grey level, e.g. used as converters ofelectrical informations into optical informations for the real timeprocessing of optical images for analog display purposes.

For reasons of clarity, throughout the remainder of the text the exampleof the liquid crystal will be used, although any other electroopticalmaterial can be considered.

FIG. 1a diagrammatically shows a matrix display with an active matrix ofa known type and FIG. 1b shows the control circuit associated with anelementary image point of said display.

FIG. 1a shows first and second insulating walls 1, 3 facing one anotherand which are kept spaced and sealed by a joint 2 arranged on theperiphery thereof. Between said walls 1, 3 is inserted a displaymaterial 4 having an optical property.

Over the inner face of one of the walls 1 are distributed n parallel rowconductors L_(i) and m parallel column conductors C_(j), which intersectwith the row conductors, i and j being integers such that 1≦i≦n and1≦j≦m, the row conductors and column conductors carrying electricalsignals appropriate for the excitation of material 4.

At the intersection 11 of each row conductor L_(i) with each columnconductor C_(j), there is a switch 5, such as a field effect transistorconnected to an electrode E_(ij) and to conductors L_(i) and C_(j).Moreover, the inner face of the other wall 3 is covered with aconductive material serving as a counterelectrode 10, which is raised toa reference potential.

An image point I_(ij) is defined in said display by the overlap regionof an electrode E_(ij) land the counterelectrode 10, electrode E_(ij)and counterelectrode 10 respectively forming the two armatures orcoatings of a capacitor, whose display material, in particular theliquid crystal placed between these armatures forms the dielectric.

In the particular case where the display material is a liquid crystalfilm, in order to prevent deterioration thereof, the counterelectrode 10is raised to a reference potential V_(R), whose value is periodicallyinverted and the column and row conductors carry electrical signals e.g.in square-wave form.

FIG. 1b shows in known manner the electric circuit diagram of a controlcircuit associated with an image point I_(ij), the latter beingrepresented by a capacitor. Thus, with the intersection of a rowconductor L_(i) and a column conductor C_(j) is associated a fieldeffect transistor 5 connected to one of the armatures of the capacitorcorresponding to electrode E_(ij). The other armature of said capacitorcorresponding to the counterelectrode is raised to the referencepotential V_(R). This capacitor makes it possible to store theinformation to be displayed at image point I_(ij).

When applying an electrical signal to row L_(i) such that the potentialapplied to the corresponding transistor 5 is equal to or higher than thethreshold voltage of said transistor, the latter is in the on state. Itthen makes it possible to transmit the electrical signal applied tocolumn C_(j) to electrode E_(ij) to which it is connected. When theelectrical signal applied to row L_(i) is such that the resultingpotential applied to the corresponding transistor 5 is below thethreshold voltage of transistor 5, the latter passes into the off stateno matter what the signal of column C_(j) and transmits no signal toelectrode E_(ij), which will therefore retain its initial charge. Thisapplies to each elementary image point of the display.

The column electrical signal transmitted to electrode E_(ij) produces anelectric field between the armatures of the capacitor constituted byelectrode E_(ij) and the counterelectrode. This field causes acollective orientation of the liquid crystal molecules between thecapacitor coatings or armatures, when the transmitted signal is above acertain threshold voltage, which corresponds to the minimum valuenecessary for exciting the liquid crystal. By using collectiveorientation and punctiform excitation of the liquid crystal molecules,an image is made to appear on the complete display.

Other matrix displays with an active matrix are known. Thus, forexample, FR-A No. 2 553 218 describes another type of matrix displaywith an active matrix. On the inner face of one of the walls of saiddisplay are arranged parallel column conductors connected to parallelcolumn electrodes and on the inner face of the other wall of the displayare arranged parallel row conductors connected by transistors toelectrodes distributed in matrix-like manner, which face the columnelectrodes, said transistors also being connected to a referencepotential V_(R).

An image point of said display is defined by the overlap zone of anelectrode with a column electrode, said two electrodes respectivelyforming the two coatings or armatures of a capacitor.

The electric diagram of the control circuit associated with an imagepoint of such a display differs from that shown in FIG. 1b through theposition of the capacitor. Thus, in this case the capacitor is connectedbetween the column conductor and the transistor, the latter also beingconnected to the corresponding row conductor and to the referencepotential V_(R). The signals applied to the row and column conductors ofthe matrix displays, like those described hereinbefore, come from acontrol means.

In known manner, a control means comprises an image memory outside thedisplay connected via interface to control means, such as a computer, animage controller connected to the external image memory by means oflogic circuits, series video signal handling circuits connected to theimage controller and video signal processing circuits connected to saidhandling circuits. The computer manages the different components of thecontrol means and transmits the informations to be displayed to theexternal image memory.

The image controller makes it possible to read by scanning theinformation stored in the external image memory. The handling circuitstransmit to the processing circuits video signals produced from signalssupplied by the image controller. These processing circuits make itpossible to transcribe the video signals from means such as ships'registers into row signals and column signals. The latter arerespectively transmitted to the row conductors and the columnconductors, so as to obtain a point-by-point display or the displaymeans.

This control means makes it possible only to write informations into theimage points of the display. In order to refresh an information at animage point, rewriting thereof takes place using the correspondinginformation in the external image memory and not in the actual imagepoint. Refreshing takes place every 20 milliseconds and consequently thefrequency of the video signals containing the informations to bedisplayed in series must be fast at approximately 5 MHz. Consequentlythe control means must be produced with rapid technology, i.e. ofmonocrystalline silicon, which suffers from the disadvantage of makingits manufacture complex and its manufacturing cost high.

Control means are also known in which the image memory is integratedinto the display and which make it possible not only to write, but alsoread and refresh informations in the image points of the display. Such ameans is for example described in GB-A No. 2 113 444.

The invention relates to a novel control means, whereof the image memoryis integrated into the display and which in particular makes it possibleto obviate the aforementioned disadvantages and which can be producedboth with fast and slow technology.

The control means according to the invention is applicable to all matrixdisplays having an active matrix and in particular to those referred tohereinbefore.

More specifically, the present invention relates to a control means fora matrix display having n·m image points arranged in matrix manner, afirst group of n row conductors and a second group of m columnconductors carrying appropriate signals for exciting an electroopticaldisplay material, each image point of the display, formed from acapacitor whose dielectric is constituted by the display material, beingassociated with a row conductor, a column conductor and a switch, eachimage point forming a memory point of the display in which it ispossible to write, read and refresh an information, characterized inthat the control means comprises m read - write circuits, each connectedto a column conductor for reading, writing and refreshing an informationat the image points associated with said column conductor, saidread-write circuits being combined into k packages, each of which has atthe most l read-write circuits, with m, l and k integers such that 1≦l≦mand 1≦k≦m, the packages of read-write circuits being connected to abidirectional data bus of l rows, the pth read-write circuits of apackage being connected to the pth row of said bus, with p being aninteger such that 1≦p≦l, the reading, writing and refreshing operationsperformed by the read-write circuits beign selected on the basis ofcontrol signals.

In the case where k and l are multiples of m, all the packagespreferably have the same number l of read-write circuits (m=l·k). In theopposite case, all the packages do not have the same number ofread-write circuits and in particular one of the packages has a smallernumber of read-write circuits than the other packages.

According to a preferred embodiment, the control means comprisesprocessing means having k processing circuits, each connected to aread-write circuit package, the reading, writing and refreshingoperations performed by the read-write circuits being selected by meansof processing circuits receiving the control signals and supplyingselection signals to the read-write circuits.

Advantageously, the control means comprises a first selection circuit,such as a decoder connected at the input to n' address rows and at theoutput to n row conductors with n≦2^(n') for selecting only one rowconductor at once.

Preferably the control means comprises a second selection circuit, suchas a decoder connected at the input to k' address rows and at the outputto k processing circuits with k≦2^(k') for selecting a single package ofcolumn conductors by choosing one processing circuit at once.

According to an embodiment of the means, each row of the bidirectionaldata bus comprises a single conductor able to carry information in twoopposite directions.

According to a constructional variant of the means, each row of thebidirectional data bus comprises first and second conductors able tocarry informations respectively in a first and a second direction, saidfirst and second directions being opposite.

The control means according to the invention does not use an externalimage memory, so that its construction is simplified. Moreover, thedisplay effected at several image points at once makes it possible forproduction to take place with slow technology, i.e. of amorphoussilicon.

According to another embodiment of the control means, the switch is atransistor.

According to an embodiment of the control means, each read-write circuitcomprises writing means which, in the information transfer direction,have a first processing circuit and a first amplifier connected to oneanother, as well as reading means connected in parallel to the writingmeans, said reading means having in the information transfer direction,a second amplifier connected both to a storage means and to a secondprocessing circuit, the storage means also being connected to the firstprocessing circuit to enable the information which has been read andstored to be refreshed.

The function of the first processing circuit is to transmit either aninformation from the data bus to the first amplifier, or an informationfrom the storage means to the first amplifier, as a function of theselection signals received by said circuit.

A function of the second processing circuit is to transmit theinformation which has been read to the data bus. Moreover, said circuitoptionally makes it possible to adapt the electrical signalcorresponding to the read information to an electrical signal of thebinary type compatible with the logic levels of the external electronicslocated at the output of the data bus. This second processing signale.g. comprises a window comparator.

According to a preferred embodiment of the control means, the firstprocessing circuit of each read-write circuit comprises a firsttransistor connected to the first amplifier and used for transferring aninformation to be written to said first amplifier, as well as a secondtransistor connected both to the first transistor and to the amplifierand also to the storage means, said second transistor being used fortransferring a read information to be refreshed, i.e. rewritten to saidfirst amplifier.

According to another preferred embodiment of the control means, thestorage means of each read-write circuit comprises a transistor and acapacitor which are connected to one another, the transistor also beingconnected to the second processing circuit and to the second amplifier,whilst the capacitor is also connected to the first processing circuit.

According to another preferred embodiment of the contorl means, one ofthe first and second amplifiers of each read-write circuit is aninverting amplifier for applying an alternative signal to the imagepoints.

The invention also relates to a control means of a matrix display havingn.m image points arranged in matrix manner, a first group of n rowconductors and a second group of m column conductors carryingappropriate signals for exciting an electrooptical display material,each image point of the display formed by a capacitor, whose dielectricis constituted by the display material beig associated with a rowconductor, a column conductor and a switch, each image pointconstituting a memory point of the display in which it is possible towrite, read and refresh an information characterized in that the controlmeans comprises m read-write circuits, each connected to a columnconductor for writing, reading and refreshing an information at theimage points associated with said column conductor, the read-writecircuits being connected to a bidirectional data bus, the reading,writing and refreshing operations performed by said read-write circuitsbeing selected on the basis of control signals, each read-write circuitcomprising writing means which, in the information transfer direction,have a first processing circuit and a first amplifier which areconnected together, as well as reading means connected in parallel tothe writing means, said reading means having in the information transferdirection, a second amplifier connected both to the storage means and toa second processing circuit, the storage means also being connected tothe first processing circuit to enable the read and stored informationto be refreshed.

The first and second processing circuits of each read-write circuit havethe same function as those described hereinbefore and consequentlypreferably have the same components. This also applies with respect tothe other components of the read-write circuit.

According to a preferred embodiment, the control means comprisesprocessing means connected to the read-write circuits, the reading,writing and refreshing operations performed by the read-write circuitsbeing selected via processing means receiving control signals andsupplying selection signals to the read-write channels.

According to another preferred embodiment the m read-write circuits arecombined into k packages, each package having at the most l read-writecircuits, with m, l and k being integers such that 1≦l≦m and 1≦k≦m, thedata bus having l rows, the pth read-write circuit of a package beingconnectedto the pth row of said bus with p being an integer such that1≦p≦l. Advantageously the means according to the invention in this casecomprises processing means having k processing circuits, each connectedto a package of read-write circuits, the reading, writing and refreshingoperations performed by said read-write circuits being selected by meansof processing circuits receiving the control signals and supplyingselection signals to the read-write circuits.

Preferably, said control means comprises a first selection circuitconnected at the input to n' address rows and at the output to n rowconductors, with n≦2^(n') for selecting a single row conductor at once.

Moreover, said control means advantageously comprises a second selectioncircuit connected at the input to address rows and at the output to theprocessing means for selecting at least one column conductor at once.

When the read-write circuits are combined into packages, said secondselection circuit makes it possible to select one package of columnconductors at once and in the opposite case, it selects a single columnconductor at once.

The invention also relates to a process for controlling a meansaccording to the invention, characterized in that for reading aninformation at an image point of the display by transmitting it from theimage point to the data bus via the read-write circuit corresponding tosaid image point or for writing an information at said image point bytransmitting it in the reverse direction, selection takes place both ofthe row conductor and the column conductor corresponding to said imagepoint and for reading an information at an image point of the display bytransmitting it from the image point to the corresponding read-writecircuit or for refreshing an information at said image point bytransmitting it in the reverse direction, selection takes place of atleast one row conductor corresponding to said image point, said reading,writing and refreshing operations being selected on the basis of controlsignals.

Other features and advantages of the invention can be best gathered fromthe following illustrative and non-limitative description and withreference to the attached FIGS. 1a to 5, wherein show:

FIGS. 1a and 1b: Already described, diagrammatically and respectively aknown matrix display with an active matrix and the electrical diagram ofthe control circuit of an image point of said display.

FIG. 2: Synoptically an example of a control means according to theinvention for a matrix display.

FIG. 3: An example of a read-write circuit according to the inventionfor an image point of the display, said circuit being associated withthe control circuit of said image point.

FIG. 4a: An exemplified timing diagram of signals applied to a rowconductor and a column conductor and the resulting signal applied to thecorresponding image point during a writing operation according to theinvention.

FIG. 4b: An exemplified timing diagram of the signals applied to a rowconductor, a column conductor and the corresponding image point duringthe reading operation according to the invention.

FIG. 5: An example of a processing circuit for the control meansaccording to the invention.

FIG. 2 shows a matrix display 9 having n·m elementary image points. Eachimage point is associated with a row conductor L_(i), a column conductorC_(j), with i and j being integers such that 1≦i≦n and 1≦j≦m and to aswitch, such as a field effect transistor. This display is e.g. of thesame type as described hereinbefore.

In FIG. 2, each group constituted by an image point and the switchassociated therewith carries the reference 7. Moreover, for reasons ofsimplicity, the reference potential V_(R) is not shown.

The control means shown in FIG. 2 comprises a first selection circuit13, such as a decoder connected to n' address rows 14 and to n rowconductors L_(i) with n≦2^(n'). The m column conductors C_(j) arecombined e.g. into k packages of in each case l column conductors, eachcolumn conductor C_(j) being connected to a read-write circuit 15. The mcolumn conductors and their corresponding read-write circuits 15 arecombined into k packages of l column conductors and l circuits 15 viaprocessing means comprising processing circuits 17, one processingcircuit 17 per package of l column conductors and l read-write circuits15. Thus, there are k processing circuits 17 in said control means.

Each read-write circuit 15 of a package is connected to the processingcircuit 17 corresponding to said package by a bus 12. Moreover, eachread-write circuit 15 of a package is connected to a row of a l rowbidirectional data bus 21, the pth read-write circuit of a package beingconnected to the pth row of the bus 21, with p being an integer suchthat 1≦p≦l. Each read-write circuit is connected to the correspondingrow of bus 21 by a bidirectional conductor 16 or by two conductors ableto carry informations in opposite directions. Throughout the remainderof the text, the particular example of a bidirectional conductor 16 willbe taken.

Each row of the bidirectional bus 21 comprises a single conductor ableto carry information in two opposite directions, or first and secondconductors able to respectively carry informations in first and seconddirections, which are opposite.

Each processing circuit 17 is also connected to not shown control means,such as a computer by a bus 20 and to a second selection circuit 19,such as a decoder. This second selection circuit 19 is connected at theinput to k' address rows 18 and at the output to k processing circuitsby conductors 18' with k≦2^(k').

The first and second selection circuits 13 and 19 are produced in knownmanner on the basis of logic gates. For example, these circuits are ofthe same type as described in DE-A No. 3 101 987. However, examples ofthe processing and read-write circuits 15 will be described in greaterdetail with reference to FIGS. 3 to 5.

Each image point I_(ij) of the display, represented by a capacitor, hasthe capacity to store information. All these capacitors form an imagememory integrated into the display and in which it is possible to write,read and refresh informations.

Each operation of refreshing information at the image points of thedisplay is preceded by an operation of reading these informations intosaid image points. These reading and refreshing operations can beperformed at the same time on all the image points of a row of pointscorresponding to a selected row conductor. During these readign andrefreshing operations, the informations are carried from the imagepoints to the corresponding read-write circuits and vice versa.

The reading operations at the image points of the display make itpossible to transmit informations from the image points to the data bus21 via corresponding read-write circuits and the writing operations atthe image points of the display make it possible to transmit informationfrom the data bus 21 to the image points via corresponding read-writecircuits can be performed independently of one another. Moreover, thesereading or writing operations can only be simultaneously performed in alimited number of image points corresponding to the image pointsassociated both with a package of selected column conductors and aselected row conductor. It is obvious that the reading operations makingit possible to transmit informations from image points to bus 21 can befollowed by operations involving the refreshing of these informations atsaid image points, in view of the fact that these informations aretransmitted via read-write circuits.

Thus, when a row conductor L_(i) and a package of l column conductorsC_(j), C_(j+1) . . . C_(j+l) are selected, the informations contained inall the image points corresponding to the row conductor L_(i) can beread, the read informations being transferred to the read-writecircuits. The informations read at image points I_(ij), I_(ij+1) . . .I_(ij+l) associated both with the row conductor and with the selectedcolumn conductors can be transferred to bus 21 and informations fromsaid bus can be written in at said image points, or in other words theinformation from the pth image point can be transmitted to the pth datarow of the bus 21 with p being an integer such that 1≦p≦l and theinformation to be written, carried by the pth data row of the bus can betransmitted to the pth column conductor of the selected package anddisplayed in the pth image point. Conversely, the informations read atthe other image points associated with the selected row conductor andwith the unselected column conductors can be rewritten into said imagepoints.

By periodically selecting each row conductor, it is possible toperiodically read and refresh the informations contained at the imagepoints of the display by transmitting the informations from the imagepoints to corresponding read-write circuits and vice versa. Moreover, inthe case where the column conductors are selected, it is possible toread or write informations at the image points corresponding both to therow conductors and to the column conductors which have been selected bytransmitting the informations from the image points to the data bus orvice versa, via read-write circuits.

The remainder of the description provides a better understanding of theoperation of the means.

In order to select a row conductor L_(i), from control equipmentsuch asa not shown computer, electric signals are supplied to n' address rows14 at the input of the selection circuit 13. A zero signal correspondsto bit "0" and a non-zero signal to bit "1". Thus, selection circuit 13will select on the basis of the n' parallel signals of the n addressrows 14, a single row conductor L_(i) from among the n row conductorsconnected thereto. Thus, selection circuit 13 supplies to the selectedrow conductor L_(i) an electrical signal, such that the resultingpotential applied to the transistors 5 connected to said conductor areequal to or greater than the threshold voltage of transistors 5 and tothe other row conductors an electrical signal such that the resultingpotential applied to the transistors connected to said conductors isbelow said threshold voltage. All the transistors 5 connected to theselected row conductor L_(i) will therefore be in the on state, whilstthe other transistors 5 associated with the other row conductors will beoff.

In the same way, for selecting a package of l column conductors C_(j) .. . C_(j+l') from the control equipment is supplied to the input ofselection circuit 19, k' parallel signals by means of the k' addressrows 18. The selection circuit 19 will now select one processing circuit17 from among the k processing circuits 17 of the means connectedthereto.

Each processing circuit 17 processes reading, writing or refreshingselection signals as a function of the signals supplied by the selectioncircuit 19 and control signals (read/write/refresh) from the controlmeans and carried by bus 20. These selection signals are then suppliedto the l read-write circuits 15 connected thereto by buses 12.

FIG. 3 shows in detail an example of a read-write circuit 15 connectedto a control circuit of the same type as described in FIG. 1b, it beingunderstood that any other control circuit of a matrix display with anactive matrix can also be used.

A read-write circuit 15 comprises a first processing circuit 25connected to an amplifier 27 in the information transfer direction froma data bus 26 of row conductor 16 to the corresponding column conductorC_(j) during a writing operation. In the same way, in the informationtransfer direction from a column conductor C_(j) to the correspondingconductor 16 during a reading operation, a read-write circuit comprisesin parallel an inverting amplifier 29 connected to a second processingcircuit 33 and a storager means 31 connected both to the invertingamplifier 29 and to the second processing circuit 33. Storage means 31is also connected to the first processing circuit 25.

The information to be written, read or rewritten at an image pointI_(ij) is constituted by the potential difference applied between thearmatures of the capacitor corresponding to said image point.

In the example of the read-write circuit of FIG. 3, the first processingcircuit 25 is realized by two transistors 24, 26 connected so as to forma switch. The storage means 31 is realized by a transistor 30 and acapacitor 32. The second processing circuit 33 is e.g. realized by aknown window comparator and which is e.g. formed by a negative feedbackamplifier or logic gates and divider bridges. It can also be realized byany device making it possible, on the basis of the information read, todetermine the state of the corresponding image point, or in other wordstransform the information read into a binary electrical signalcompatible with the external electronics connected to bus 21 (a zeroelectrical signal corresponding to an undisplayed state and a non-zeroelectrical signal to a displayed state).

Capacitor 32 is connected on the one hand to transistor 30 andtransistor 26 and on the other hand to earth or ground. Moreover,transistor 30 is connected both to the processing circuit 33 and toamplifier 29, whilst transistor 26 is connected both to transistor 24and to amplifier 27.

The selection signals for a writing or refreshing operation for aninformation at image oint I_(ij) and the selection signals of a readingoperaton at said image point I_(ij) are processed by the processingcircuit 17 associated with the read-write circuit 15. These selectionsignals are constituted by electrical signals applied to circuit 15 at Eand 27 for a writing operation and at L and 35 for a reading operationtransferring the information from the image point to the bus 21 by theread-write circuit, as well as at R and 37 for a refreshing operationand at L for a reading operation transmitting the information from theimage point to the read-write circuit and more specifically to thecapacitor 32 of the storage means.

In order to carry out a writing operation at image I_(ij) correspondingto row conductor L_(i) and to column conductor C_(j), the row conductorL_(i) and column conductor C_(j) are consequently selected. Thetransistor 5 associated with said image point is then in the one state.Moreover, a non-zero electrical signal at E is supplied to thetransistor 24 of processing circuit 25 and a non-zero electrical signalat 37 to amplifier 27, in such a way that transistor 24 and amplifier 27are in the on state. The information carried in the form of anelectrical signal by conductor 16 and coming from the corresponding rowof data bus 21 will pass through transistor 24 and is amplified byamplifier 27 before being transmitted to conductor C_(j). As transistor5 is in the on state, the signal will be transmitted to the capacitorcorresponding to image point I_(ij) by said transistor 5. Thus, betweenthe capacitor armatures is established a potential differenceproportional to the transmitted signal, said potential differenceproducing an electric field, which will excite the molecules of theliquid crystal inserted between said capacitor armatures. Theinformation displayed at point I_(ij) is consequently dependent on thesignal transmitted by the row of the bidirectional data bus 21.

In order to read an information at image point I_(ij) and transfer it tothe row of corresponding bus 21, the corresponding row conductor andcolumn conductor are selected and a non-zero electrical signal at 35 istransmitted to the processing circuit 33 and a non-zero electricalsignal at L to the transistor 30 of storage means 31, so as to bringcircuit 33 and transistor 30 into the on state. The informationcontained by capacitor I_(ij) in the form of an electrical field istransferred to inverting amplifier 29, amplifier 27 being in the highimpedance state due to the fact that it has not received an electricalsignal at 37. At the output of amplifier 29, the signal from thecapacitor is inverted and transmitted on the one hand to storage means31 and on the other to processing circuit 33. Transistor 30 of thestorage means being in the on state, it consequently transmits tocapacitor 32 the signal which has been read, in order to temporarilystore the information contained by said signal. Furthermore, theprocessing circuit 33 which is also in the on state will transmit thesignal read to the corresponding row of the bidirectional data bus 21via conductor 16.

In order to read an information at image point I_(ij) corresponding to arow conductor L_(i) and to a column conductor C_(j) and transfer it tocapacitor 32, it is sufficient to select the corresponding row conductor(whereby the column conductor C_(j) may or may not be selected) andsupply a non-zero electrical signal at L to transistor 30 so as to bringit into the on state. Transistor 30 then transmits the information readto capacitor 32.

The information contained in capacitor 32 in the form of an electricalfield makes it possible to refresh the corresponding image point byrewriting said stored information. Thus, for rewriting an information atimage point I_(ij), it is merely necessary to select the correspondingrow conductor L_(i) (whereby the column conductor C_(j) may or may notbe selected) and supply a non-zero electrical signal at R in order tobring to the on state the transistor 26 of processing circuit 25 and anon-zero electrical signal at 37 to bring amplifier 27 into the onstate. As transistors 24 and 30 are off, the information will passthrough transistor 26 and amplifier 27 before being transmitted to thecorresponding column conductor C_(j). The information initiallycontained in capacitor I_(ij) in the form of an electrical signal willbe rewritten with a reverse polarity due to the inversion of the signalperformed by the inverting amplifier 29.

Although amplifier 29 is of the inverting type, it would also bepossible for it to be of the non-inverting type, whilst making amplifier27 of the inverting type.

The polarity of the corresponding signal will be reversed for eachrefreshing of the information. The application of an alternative signalto capacitor I_(ij) consequently makes it possible to increase the lifeof the display material, such as the liquid crystal placed between thecapacitor armatures. Refreshing is e.g. carried out on a period or cycleof approximately 20 ms.

The timing diagrams of FIGS. 4a and 4b show examples of exciting signalsV_(Li), V_(Cj) respectively applied to a row conductor L_(i) and to acolumn conductor C_(j) during a writing operation (FIG. 4a) and during areading operation (FIG. 4b) of an information at the corresponding imagepoint and the resulting signals V_(ij) at the image point. The excitingsignals shown are impulse square-wave signals, but other signals, suchas sinusoidal signals could also be applied.

Signal V_(Li) applied to the row conductor L_(i) is non-zero for a timeT_(L), called the row time, which is equal to the addressing period Tdivided by the number of row conductors n of the means. The signalV_(Li) is zero outside said row time T_(L). Thus, the transistorsassociated with the row conductor L_(i) are only in the on state duringthe non-zero pulse of signal V_(Li), i.e. for a time T_(L).

Thus, during a writing operation (FIG. 4a), with transistor 5 associatedwith image point I_(ij) corresponding to a row conductor L_(i) and acolumn conductor C_(j) in the on state, it transmits signal V_(Cj)applied to column C_(j) to the capacitor I_(ij) corresponding to theimage point. When signal V_(Cj) is non-zero, it establishes a potentialdifference equal to the signal V_(Cj) -V_(R) between the capacitorarmatures. The resulting signal V_(ij) seen by the liquid crystalconsequently has an amplitude equal to V_(Cj) -V_(R). Throughout theaddressing time T, the capacitor armatures remain charged, so thatduring said time T, the image point retains the information writtenduring the row time T_(L), except for the charge leaks.

A refreshing operation consists of writing the information read.Consequently it takes place as described hereinbefore the signals V_(Cj)and V_(ij) being the same, but of reverse polarity to that of thepreceding period or cycle.

During a reading operation (FIG. 4b), in the same way as for a writingor refreshing operation, the transistor associated with the image pointin which the information has to be read must be in the on state.Therefore the reading operation takes place at the time when the signalV_(Li) applied to the row conductor L_(i) is non-zero.

An equipartition of the charge C_(ij) (image of signal V_(ij)) containedin capacitor I_(ij) into said same capacitor and into a possibleparasitic capacitance associated with the column conductor C_(j)produces a signal V_(Cj), which is then transferred by the columnconductor C_(j) to read-write circuit 15. Following the reading ofsignal V_(ij) contained in the capacitor, the potential differencebetween the armatures of said capacitor is not zero. It decreases from amaximum level 40 obtained during a writing operation to a value equal toV_(Cj) -V_(R).

FIG. 5 shows an example of the processing circuit 17 of a control meansaccording to the invention. Circuit 17 has a logic gate 51 such as anAND gate having two inputs and a logic gate 53, such as a NOR gate,which also has two inputs. The two inputs of gate 51 are respectivelyconnected by a conductor 45' to the corresponding conductor 18' ofselection circuit 19 and to bus 20 by a conductor 41. The two inputs ofgate 53 are respectively connected to the output of gate 51 and to bus20 via a conductor 43. Moreover, said circuit 17 has a conductor 45connected to selection circuit 19 via the corresponding conductor 18'and two conductors 47, 49 respectively connected to bus 20.

At the output, conductor 45, gate 51, gate 53, conductor 47 andconductor 49 are respectively connected at 35, E, R, L and 37 of all theread-write circuits associated with said processing circuit.

The signals applied at L and 37 carried by condcutors 47 and 49 are notdependent on the output signal of selection circuit 19. Therefore thesesignals are identical for all the read-write circuits of the controlmeans and are solely dependent on the control signals.

The control signals carried by conductors 47, 49 undergo no electronicprocessing in circuit 17 shown in FIG. 5, but obviously this example isnot limitative. Thus, it would be possible to use in circuit 17components of different types for processing said signals.

For the clarity of the description, the electrical signals have beenlikened to binary signals of high level "1" and low level "0".

The electrical signals supplied on conductors 41,43, 47 and 49 by bus 20are dependent on the operations to be validated and the signal carriedby conductors 45, 45' corresponds to a high level when the processingcircuit is selected and a low level in the opposite case.

To validate an operation of readig the data of the image points at theread-write circuits, conductor 47 must carry a signal with a high level"1". To validate an operation of reading the data of the image points atdata bus 21 via read-write circuits, conductors 47 and 45 mustrespectively carry a high level signal. To validate a writing operationof data of data bus 21 at the image points by the read-write circuits,the signals carried by conductors 45' and 41 must both be at high levelin order that the output signal of gate 51 is at high level. To validatea refreshing operation, the output signal of gate 51 must be at lowlevel, as must the signal carried by conductor 43, so that the outputsignal of gate 53 is at high level. Moreover, to validate a writing orrefreshing operation, conductor 49 must carry a signal at a high level.

Thus, with said circuit 17, when a writing operation is validated, arefreshing operation cannot be validated. Conversely, when a writingoperation is not validated, particularly in the case where theprocessing circuit is not selected and the signal of conductor 43 is atlow level, the refreshing operation can be validated.

The control means according to the invention can easily be integratedinto a conventional display with ancillary means.

Moreover, as a result of the integration of the image memory into thedisplay, it makes it possible to achieve considerable economiesparticularly with respect to an image memory outside the display, ascreen controller and circuits for handling or producing video signalsused in the prior art control means. It also makes it possible to readinformation contained in said integrated memory and therefore to refreshthe information read. Moreover, the writing operations can be carriedout in l image points at once and refreshing in m image points at thesame time. The means according to the invention can be produced withslow technology, particularly amorphous silicon.

The above description with respect to the selection of column conductorsin packages is not limitative and the control means according to theinvention is also applicable to column conductors selected in unitarymanner.

Moreover, the examples of the different circuits described hereinbeforeof the means according to the invention are in no way limitative. Thus,other modifications can be made to those circuits without passing beyondthe scope of the invention. It would have been possible for thebidirectional data bus 21 to be connected to the read-write circuit 15via processing circuits 17 and the latter would then have transferredinformations from bus 21 to the read-write circuits 15 and vice versa.Moreover, the selection circuits 13, 19 described in FIG. 2 are notindispensable to the operation of the means according to the invention,but make it possible to reduce the number of connections.

We claim:
 1. Control means for a matrix display (9) having nxm imagepoints arranged in matrix manner, a first group of n row conductors(L_(i)) and a second group of m column conductors (C_(j)) carryingappropriate signals for exciting an electrooptical display material,each image point (I_(ij)) of the display, formed from a capacitor whosedielectric is constituted by the display material, being associated witha row conductor (L_(i)), a column conductor (C_(j)) and a switch (5),each image point forming a memory point of the display in which it ispossible to write, read and refresh an information, characterized inthat the control means comprises m read-write circuits (15), eachconnected to a column conductor (C_(j)) for reading, writing andrefreshing an information at the image points associated with saidcolumn conductor (C_(j)), said read-write circuits (15) being combinedinto k packages, each of which has at the most l read-write circuits,with m, l and k integers such that 1<l<m and l<k<m, the packages ofread-write circuits being connected to a bidirectional data bus (21) ofl rows, the pth read-write circuits (15) of each package being connectedto the pth row of said bus, with p beig an integer such that 1≦p≦l, thereading, writing and refreshing operations performed by the read-writecircuits being selected on the basis of control signals (20).
 2. Controlmeans according to claim 1, characterized in that it comprisesprocessing means having k processing circuits (17), each connected to apackage of read-write circuits (15), the reading, writing and refreshingoperations performed by the read-write circuits being selected by meansof processing circuits receiving the control signals (20) and supplyingselection signals (35, E, R, L, 37) to the read-write circuits. 3.Control means according to claim 1, characterized in that it comprises afirst selection circuit (13) connected at the input to n' address rows(14) and at the output to n row conductors (L_(i)) with n≦2^(n') forselecting a single row conductor at once.
 4. Control means according toclaim 2, characterized in that it comprises a second selection circuit(19) connected at the input to k' address rows (18) and at the output tok processing circuits (17), with k≦2^(k') for selecting a single packageof column conductors (C_(j)) by choosing a single processing circuit(17) at once.
 5. Control means according to claim 1, characterized inthat each read-write circuit (15) comprises writing means (25, 27)which, in the information transfer direction, have a first processingcircuit (250 and a first amplifier (27) which are interconnected, aswell as reading means (29, 31, 33) connected in parallel to the writingmeans, said reading means having in the information transfer direction asecond amplifier (29) connected both to a storage means (31) and to asecond processing circuit (33), the storage means also being connectedto the first processing circuit (25) to permit the refreshing of theinformation read and stored, the first processing circuit transmittingan information from the data bus or storage means to the first amplifierand the second processing circuit transmitting an information from thesecond amplifier to the data bus.
 6. Control means according to claim 5,characterized in that the first processing circuit (25) comprises afirst transistor (24) connected to the first amplifier (27) and used fortransferring an information to be written to said first amplifier and asecond transistor (26) connected on the one hand to the first transistor(24) and the first amplifier (27) and on the other hand to the storagemeans (31), said second transistor (26) transferring a read informationto be refreshed to said first amplifier.
 7. Control means according toclaim 5, characterized in that the storage means (31) comprises atransistor (30) and a capacitor (32) which are interconnected, saidtransistor also being connected to the second processing circuit (33)and a second amplifier (29), whilst capacitor (32) is also connected tothe first processing circuit (25).
 8. Control means according to claim5, characterized in that one of the first and second amplifiers (27, 29)is an inverting amplifier for applying an alternative signal to theimage points.
 9. A control means of a matrix display (9) having n·mimage points arranged in matrix manner, a first group of n rowconductors (L_(i)) and a second group of m column conductors (C_(j))carrying appropriate signals for exciting an electrooptical displaymaterial, each image point (I_(ij)) of the display formed by acapacitor, whose dielectric is constituted by the display material beingassociated with a row conductor (L_(i)), a column conductor (C_(j)) anda switch (5), each image point constituting a memory point of thedisplay in which it is possible to write, read and refresh aninformation characterized in that the control means comprises mread-write circuits (15), each connected to a column conductor (C_(j))for writing, reading and refreshing an information at the image pointsassociated with said column conductor (C_(j)), the read-write circuits(15) being connected to a bidirectional data bus (21), the reading,writing and refreshing operations performed by said read-write circuits(15) being selected on the basis of control signals (20), eachread-write circuit comprising writing means (25, 27) which, in theinformation transfer direction, have a first processing circuit (25) anda first amplifier (27) which are connected together, as well as readingmeans (29, 31, 33) connected in parallel to the writing means, saidreading means having in the information transfer direction, a secondamplifier (29) connected both to the storage means (31) and to a secondprocessing circuit (33), the storage means also being connected to thefirst processing circuit (25) to enable the read and stored informationto be refreshed, the first processing circuit transmitting informationfrom the data bus or storage means to the first amplifier and the secondprocessing circuit transmitting an information from the second amplifierto the data bus.
 10. Control means according to claim 9, characterizedin that it comprises processing means (17) connected to read-writecircuits (15), the reading, writing and refreshing operations performedby the read-write circuits being selected by a processing meansreceiving control signals and supplying selection signals (35, E, R, L,37) to the read-write circuits.
 11. Control means according to claim 9,characterized in that the m read-write circuits are combined into kpackages, each package having at the most l read-write circuits with m,l and k integers such that 1≦l≦m and 1≦k≦m, the data bus (21) having lrows, the pth read-write circuit of a package being connected to the pthrow of said bus with p being an integer such that 1≦p≦l.
 12. Controlmeans according to claim 11, characterized in that it comprisesprocessing means having k processing circuits (17), each connected to apackage of read-write circuits (15), the reading, writing and refreshingoperations performed by the read-write circuits being selected by meansof processing circuits receiving the control signals (20) and supplyingthe selection signals (35, E, R, L, 37) to the read-write circuits. 13.Control means according to claim 9, characterized in that it comprises afirst selection circuit (13) connected at the input to n' address rows(14) and at the output to n row conductors (L_(i)), with n≦2^(n'), forselecting a single row conductor at once.
 14. Control means according toany one of the claims 10 and 12, characterized in that it comprises asecond selection circuit (19) connected at the input to address rows(18) and at the output to processing means (17) for selecting at leastone column conductor (C_(j)) at once.
 15. Control means according toclaim 9, characterized in that the first processing circuit (25)comprises a first transistor (24) connected to the first amplifier (27)and use for transferring an information to be written to said firstamplifier, as well as a second transistor (26) connected on the one handto the first transistor (24) and to the first amplifier (27) and on theother handn to the storage means (31), said second transistor (26) beingused for transferring a read information to be refresehd to said firstamplifier.
 16. Control means according to claim 9, characterized in thatthe storage means (31) comprises a transistor (30) and a capacitor (32)which are interconnected, the transistor also being connected to thesecond processing circuit (33) and to the second amplifier (29), whilstcapacitor (32) is also connected to the first processing circuit (25).17. Control means according to claim 9, characterized in that one of thefirst and second amplifiers (27, 29) is an inverting amplifier forapplying an alternative signal to the image points.
 18. Control processfor the control means according to any one of the claims 1 and 9,characterized in that for reading an information at an image point(I_(ij)) of the display by transmitting it from the image point to thedata bus (21) via the read-write circuit (15) corresponding to saidimage point or for writing an information at said image point bytransmitting it in the reverse direction, selection takes place both ofthe row conductor (L_(i)) and the column conductor (C_(j)) correspondingto said image point and for reading an information at an image point ofthe display by transmitting it from the image point to the correspondingread-write circuit or for refreshing an information at said image pointby transmitting it in the reverse direction, selection takes place of atleast one row conductor corresponding to said image point, said reading,writing and refresing operations being selected on the basis of controlsignals.
 19. A control means for a matrix display having nxm imagepoints arranged in matrix manner, a first group of n row conductors anda second group of m column conductors carrying appropriate signals forexciting an electro-optical display material, each image point of thedisplay, forming from a capacitor whose dielectric is constituted by thedisplay material, being associated with a row conductor, a columnconductor and a switch, each point forming a memory point of the displayin which it is possible to write, read and refresh an information,wherein said control means comprises m read-write circuits eachconnected to a column conductor for reading, writing and refreshing aninformation at the image points associated with said column conductor,said read-write circuits being combined into k packages, each of whichhas at the most l read-write circuits, with m, l and k integers suchthat 1<l<m and 1<k <m, the packages of read-write circuits beingconnected to a bidirectional data bus of l rows, the pth read-writecircuits of each package being connected to the pth row of said bus,with p being an integer such that 1≦p≦l, the reading, writing andrefreshing operations performed by the read-write circuits beingselected on the basis of control signals, said control means furthercomprising processing means having k processing circuits, each connectedto a package of read-write circuits, the reading, writing and refreshingoperations formed by the read-write circuits being selected by means ofsaid processing circuits receiving said control signals and supplyingselection signals to the read-write circuits,a first selection circuitconnected at the input to n' address rows and at the output to n rowconductors with n23 2^(n') for selecting a single row conductor at onetime, a second selection circuit connected at the input to k' addressrows and the output to k processing circuits, with k≦2^(k') forselecting a single package of column conductors by choosing a singleprocessing circuit at one time.
 20. A control means of a matrix displayhaving nxm image points arranged in matrix manner, a first group of nrow conductors and a second group of m column conductors carryingappropriate signals for exciting an electro-optical display material,each image point of the display formed by a capacitor, whose dielectricis constituted by the display material being associated with a rowconductor, a column conductor and a switch and each image pointconstituting a memory point of the display in which it is possible towrite, read and refresh an information wherein said control meanscomprises m read-write circuits, each connected to a column conductorfor writing, reading and refreshing an information at the image pointsassociated with said column conductor, the read-write circuits beingconnected to a bidirectional data bus, the reading, writing andrefreshing operations performed by said read-write circuits beingselected on the basis of control signals, each read-write circuitcomprising writing means which, in the information transfer direction,have a first processing circuit and a first amplifier which areconnected together, as well as reading means connected in parallel tothe writing means, said reading means having in the information transferdirection, a second amplifier connected both to the storage means and toa second processing circuit, the storage means being also connected tothe first processing circuit to enable the read and store information tobe refreshed, the first processing circuit transmitting an informationfrom the data bus or storage means to the first amplifier and the secondprocessing circuit transmitting an information from the second amplifierto the data bus, said control means further comprising processing meansconnected to read-write circuits, the reading, writing and refreshingoperations performed by the read-write circuits being selected by saidprocessing means receiving control signals and supplying selectionsignals to the read-write circuits, said control means furthercomprising a first selection circuit connected at the input to n'address rows and at the output to n row conductors, with n≦2^(n'), forselecting a single row conductor at one time, and a second selectioncircuit connected at the input to address rows and at the output to saidprocessing means for selecting at least one column conductor at onetime.